The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for run-time task-level dynamic energy management.
Power optimization is directed to optimizing (reducing) power consumption of a digital design, such as that of an integrated circuit, while preserving functionality. That is, the increasing speed and complexity of today's integrated circuit designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. To meet this challenge, researchers have developed many different design techniques to reduce power.
One key feature that led to the success of complementary metal-oxide semiconductor, or CMOS, technology is intrinsic low-power consumption. With CMOS technology, circuit designers and electronic design automation (EDA) tools are able to concentrate on maximizing circuit performance and minimizing circuit area. Another interesting feature of CMOS technology is its nice scaling properties, which has permitted a steady decrease in the feature size, allowing for more and more complex systems on a single chip, working at higher clock frequencies.
However, in light of the newest technologies, the increasing size of integrated circuits has contributed to the rise of power as a major design parameter. In fact, power consumption is regarded as the limiting factor in the continuing scaling of CMOS technology. To respond to this challenge, in the last decade or so, intensive research has been put into developing tools and techniques that address the problem of power optimization. But these techniques, system-wide and external, have often led to non-optimal results when deployed. That is, current power optimization techniques are currently blind to numerous aspects, such as applications and application workload.